1. Field of the Invention
The present invention relates to an image sensor, and more particularly, to a method of fabricating a CMOS image sensor. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for enhancing image sensor characteristics.
2. Discussion of the Related Art
An image sensor is a semiconductor device that converts an optical image into an electrical signal. A complementary MOS (CMOS) image sensor includes a photosensing device, such as a photodiode, and a CMOS logic circuit including a plurality of MOS transistors corresponding to the number of pixels. The CMOS image sensor is generally fabricated using CMOS technology. To enhance photosensitivity of the image sensor, its fill factor may be improved, but since the logic circuit (or other peripheral structures) consumes some area, there are limits to improving the fill factor. Alternatively, microlenses may be used to direct incident light onto the photosensing areas only. Another approach to photosensitivity enhancement is to shorten the traveling distance of a light signal passing through a microlens layer to be transmitted to an underlying photodiode.
To provide an image sensor with color separation capability, a color filter array including a plurality of color filters is arranged, together with the microlenses, over the respective photosensing devices. The color filter array and microlenses are disposed in a photodiode region, separate from and adjacent to a pad region for forming a plurality of wiring layer interconnections of the CMOS logic circuit, which may be configured for a three-transistor (3T) or for a four-transistor (4T) CMOS image sensor. A 3T CMOS image sensor consists of one photodiode and three transistors per pixel, and a 4T CMOS image sensor consists of one photodiode and four transistors per pixel.
Referring to FIG. 1, a unit pixel of a general 3T-type CMOS image sensor consists of one photodiode PD and three NMOS transistors Rx, Dx, and Sx. The cathode of the photodiode PD is connected to the drain of the first NMOS transistor Rx and the gate of the second NMOS transistor Dx. The sources of the first and second NMOS transistors Rx and Dx are connected to a power line supplying a reference voltage VR, and a gate of the first NMOS transistor Rx is connected to a reset line supplying a reset signal. The source of the third NMOS transistor Sx is connected to the drain of the second NMOS transistor Dx. The drain of the third NMOS transistor Sx is connected to a read circuit (not shown). The gate of the third NMOS transistor Sx is connected to a row select line supplying a select signal, which generally enables reading and/or sensing a signal generated by the photodiode and at least the second NMOS transistor Dx.
Referring to FIG. 2, an active region 10 is defined in a unit pixel of the general 3T-type CMOS image sensor. A photodiode 20 is formed on a relatively large and/or wide portion of the active region 10, and other parts of the active region are overlapped by three gate electrodes 120, 130, and 140, to configure a reset transistor Rx, a drive transistor Dx, and a select transistor Sx, respectively. The exposed portions of the active region 10 of each transistor are doped with impurity ions to become corresponding source/drain regions. A power voltage Vdd is applied to the source/drain regions between the reset and drive transistors Rx and Dx. A plurality of signal lines (not shown) are respectively connected to the gate electrodes and connect the source/drain region of the select transistor Sx a read circuit (not shown). A pad is provided to each of the signal lines to connect to an external drive circuit.
FIGS. 3A-3D respectively illustrate sequential process steps of a method of fabricating a contemporary CMOS image sensor.
Referring to FIG. 3A, a semiconductor substrate (not shown) is divided into a photodiode region and a pad region, and a plurality of photodiodes 20 for generating charges according to intensity of incident light are formed in the photodiode region. A first insulating interlayer 100 is formed over the substrate including the photodiodes 20. A tetra-ethyl-ortho-silicate oxide layer 101 is formed on the first insulating interlayer 100. A metal pad 102 for each signal line is formed on the oxide layer 101. In doing so, the metal pad 102, which generally comprises aluminum, may be formed from the same metal layer as the gate electrodes 120, 130, and 140 (see FIG. 2) using the same material. A second insulating interlayer 103 is formed over the substrate including the metal pad 102.
Referring to FIG. 3B, the second insulating interlayer 103 is coated with a first layer of photoresist, which is patterned by exposure and development steps to form a photoresist pattern 104 for exposing a portion of the second insulating interlayer 103 over the metal pad 102. The exposed portion of the second insulating interlayer 103 is selectively etched using the first photoresist pattern 104 as an etch mask to form a pad opening 105 on the metal pad 102.
Referring to FIG. 3C, the first photoresist pattern 104 is removed. The semiconductor substrate including the pad opening 105 is coated with a second layer of photoresist, which is selectively patterned by exposure and development to form a second photoresist pattern 106 for exposing the photodiode region. The second insulating interlayer 103 and the oxide layer 101 are selectively etched in the photodiode region, using the second photoresist pattern 106 as a mask. This etching is to reduce a distance between the photodiodes 20 and a microlens to be formed later.
Referring to FIG. 3D, the second photoresist pattern 106 is removed. A plurality of hemispherical microlenses 107 are formed on the first insulating interlayer 100 in the photodiode area, each microlens 107 corresponding to a unique photodiode 20, by coating the substrate with a microlens material layer, patterning the microlens material layer, and reflowing the patterned microlens material.
Since the microlens and a color filter layer are formed after completion of the pad opening, a vertical slope may be formed on an edge of the photodiode region. Hence, striation occurs, which may degrade the uniformity of the microlens thickness. Moreover, photolithography and etching processes, for reducing the distance between the microlens and the photodiode, are separately and/or additionally carried out, thereby increasing the number of process steps.